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This read-only register is provided for compatibility with the AT disk drive interface and can be used for
confirming the drive status. It is recommended that this register is not mapped into the host’s I/O space
because of potential conflicts on Bit 7. The bits are defined as follows:
7.13.1 Bit 7
This bit is don’t care.
7.13.2 Bit 6 (-WTG)
This bit is ‘0’ when a write operation is in progress; otherwise, it is ‘1’.
7.13.3 Bit 5 (-HS3)
This bit is the negation of bit 3 in the Drive/Head register.
7.13.4 Bit 4 (-HS2)
This bit is the negation of bit 2 in the Drive/Head register.
7.13.5 Bit 3 (-HS1)
This bit is the negation of bit 1 in the Drive/Head register.
7.13.6 Bit 2 (-HS0)
This bit is the negation of bit 0 in the Drive/Head register.
7.13.7 Bit 1 (-nDS1)
This bit is ‘0’ when drive 1 is act ive and selected.
7.13.8 Bit 0 (-nDS0)
This bit is ‘0’ when the drive 0 is active and selected.
Table 33: Drive Address Register
D7
X
D6
-WTG
D5
-HS3
D4
-HS2
D3
-HS1
D2
-HS0
D1
-nDS1
D0
-nDS0
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
P-120_data_sheet_PA-QxBO_Rev100.doc
Page 36 of 76
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